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d a t a sh eet product speci?cation supersedes data of 2000 mar 29 file under integrated circuits, ic01 2000 jul 31 integrated circuits uda1342ts audio codec
2000 jul 31 2 philips semiconductors product speci?cation audio codec uda1342ts contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 system clock 8.2 adc analog front-end 8.2.1 application with 2 v (rms) input 8.2.2 double differential mode 8.3 decimation filter (adc) 8.4 digital mixer (adc) 8.5 interpolation filter (dac) 8.6 mute 8.7 digital mixer (dac) 8.8 noise shaper 8.9 filter stream dac 8.10 digital interface 8.11 sampling speed 8.12 power-on reset 8.13 control modes 8.14 static pin mode 8.14.1 system clock setting select 8.14.2 digital interface format select 8.14.3 adc input channel select 8.15 l3-bus interface 8.15.1 introduction 8.15.2 device addressing 8.15.3 register addressing 8.15.4 data write mode 8.15.5 data read mode 8.16 i 2 c-bus interface 8.16.1 addressing 8.16.2 slave address 8.16.3 register address 8.16.4 write cycle 8.16.5 read cycle 9 register mapping 9.1 reset 9.2 quick mode switch 9.3 bypass mixer dc filter 9.4 dc filter 9.5 adc mode 9.6 adc polarity 9.7 system clock frequency 9.8 data format 9.9 dac power control 9.10 input oversampling rate 9.11 dac polarity 9.12 dac mixing position switch 9.13 dac mixer 9.14 silence detection period 9.15 multi purpose output 9.16 mode 9.17 bass boost 9.18 treble 9.19 silence detector switch 9.20 mute 9.21 quick mute mode 9.22 de-emphasis 9.23 adc input amplifier gain 9.24 dac volume control 9.25 dac mixer volume control 9.26 adc mixer gain control 10 limiting values 11 handling 12 quality specification 13 thermal characteristics 14 dc characteristics 15 ac characteristics 16 timing 17 application information 18 package outline 19 soldering 19.1 introduction to soldering surface mount packages 19.2 reflow soldering 19.3 wave soldering 19.4 manual soldering 19.5 suitability of surface mount ic packages for wave and reflow soldering methods 20 data sheet status 21 definitions 22 disclaimers 23 purchase of philips i 2 c components
2000 jul 31 3 philips semiconductors product speci?cation audio codec uda1342ts 1 features general 2.7 to 3.6 v power supply 5 v tolerant digital inputs high pin compatibility with uda1341ts 24 bits data path selectable control via l3-bus interface, i 2 c-bus interface or static pin control; choice of 2 device addresses in l3-bus and i 2 c-bus mode supports sample frequencies from 16 to 110 khz separate power control for adc and dac adc and programmable gain amplifiers (pga) plus integrated high-pass filter to cancel dc offset integrated digital filter plus dac digital silence detection no analog post filtering required for dac slave mode only applications easy application. multiple format data interface i 2 s-bus, msb-justified and lsb-justified format compatible 1f s to 4f s input and 1f s output format data rate. dac digital sound processing separate digital logarithmic volume control for left and right channels in l3-bus mode or i 2 c-bus mode digital tone control, bass boost and treble in l3-bus mode or i 2 c-bus mode digital de-emphasis for sample frequencies of 32, 44.1, 48 and 96 khz in l3-bus mode or i 2 c-bus mode soft or quick mute in l3-bus mode or i 2 c-bus mode output signal polarity control in l3-bus mode or i 2 c-bus mode digital mixer for adc output signal and digital serial input signal. advanced audio configuration 4 channel (2 stereo) single-ended inputs with programmable gain amplifiers and 2 channel (1 stereo) single-ended outputs configuration output signal polarity control in l3-bus mode or i 2 c-bus mode high linearity, wide dynamic range, low distortion double differential input configuration for enhanced adc sound quality. 2 applications eminently suitable for minidisc (md) home and portable applications. 3 general description the uda1342ts is a single-chip 4 channel analog-to-digital converter and 2 channel digital-to-analog converter with signal processing features employing bitstream conversion techniques. the low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. the uda1342ts supports the i 2 s-bus data format with word lengths of up to 24 bits, the msb-justified data format with word lengths of up to 24 bits and the lsb-justified serial data format with word lengths of 16, 20 and 24 bits. the device also supports a combination of the msb-justified output format and the lsb-justified input format. the uda1342ts has special sound processing features in the playback mode such as de-emphasis, volume, mute, bass boost and treble, which can be controlled by the microcontroller via the l3-bus or i 2 c-bus interface.
2000 jul 31 4 philips semiconductors product speci?cation audio codec uda1342ts 4 quick reference data symbol parameter conditions min. typ. max. unit supplies v dda(adc) adc analog supply voltage 2.7 3.0 3.6 v v dda(dac) dac analog supply voltage 2.7 3.0 3.6 v v ddd digital supply voltage 2.7 3.0 3.6 v i dda(adc) adc analog supply current 1 adc + 1 pga enabled - 10.0 - ma 2 adcs + 2 pgas enabled - 20.0 - ma all adcs + all pgas power-down - 200 -m a i dda(dac) dac analog supply current operating - 6.0 - ma dac power-down - 250 -m a i ddd digital supply current operating - 9.0 - ma adc power-down - 4.5 - ma dac power-down - 5.5 - ma t amb ambient temperature - 40 - +85 c analog-to-digital convertor v i(rms) input voltage (rms value) at 0 db (fs) digital output - 0.9 - v (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz normal mode at - 1db -- 90 - db at - 60 db; a-weighted -- 40 - db double differential at - 1db -- 93 - db at - 60 db; a-weighted -- 41 - db (thd+n)/s 96 total harmonic distortion-plus-noise to signal ratio at f s =96khz normal mode at - 1db -- 84 - db at - 60 db; a-weighted -- 39 - db s/n 48 signal-to-noise ratio at f s = 48 khz normal mode; v i = 0 v; a-weighted - 100 - db double differential mode; v i = 0 v; a-weighted - 101 - db s/n 96 signal-to-noise ratio at f s = 96 khz normal mode; v i = 0 v; a-weighted - 99 - db a cs channel separation - 100 - db
2000 jul 31 5 philips semiconductors product speci?cation audio codec uda1342ts note 1. the output voltage of the dac is proportionally to the dac power supply voltage. 5 ordering information digital-to-analog convertor v o(rms) output voltage (rms value) at 0 db (fs) digital input; note 1 - 0.9 - v (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s =48khz at 0 db -- 90 - db at - 60 db; a-weighted -- 40 - db (thd+n)/s 96 total harmonic distortion-plus-noise to signal ratio at f s =96khz at 0 db -- 83 - db at - 60 db; a-weighted -- 39 - db s/n 48 signal-to-noise ratio at f s = 48 khz code = 0; a-weighted - 100 - db s/n 96 signal-to-noise ratio at f s = 96 khz code = 0; a-weighted - 99 - db a cs channel separation - 100 - db type number package name description version uda1342ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 symbol parameter conditions min. typ. max. unit
2000 jul 31 6 philips semiconductors product speci?cation audio codec uda1342ts 6 block diagram handbook, full pagewidth mgt016 adc pga pga pga 6 8 18 16 17 19 25 12 15 14 13 vinl2 v ssd v ddd datao bck ws datai voutl 27 24 26 voutr sysclk 21 static l3data l3clock l3mode vinr2 10 11 dc-cancellation filter decimation filter digital mixer (adc) digital interface l3-bus/ i 2 c-bus interface adc dac v ssa(dac) v dda(dac) v ref dac interpolation filter noise shaper digital mixer (dac) dsp features 20 test1 31 v dda(adc) v ssa(adc) 75 v adcp v adcn uda1342ts 28 pga 23 qmute 22 status 9 ipsel adc 2 4 vinl1 vinr1 adc fig.1 block diagram.
2000 jul 31 7 philips semiconductors product speci?cation audio codec uda1342ts 7 pinning symbol pin type description v ssa(adc) 1 analog ground pad adc analog ground vinl1 2 analog input pad adc input left 1 v dda(adc) 3 analog supply pad adc analog supply voltage vinr1 4 analog input pad adc input right 1 v adcn 5 analog pad adc reference voltage n vinl2 6 analog input pad adc input left 2 v adcp 7 analog pad adc reference voltage p vinr2 8 analog input pad adc input right 2 ipsel 9 5 v tolerant digital input pad channel select input: input left 1 and right 1 or input left 2 and right 2 v ddd 10 digital supply pad digital supply voltage v ssd 11 digital ground pad digital ground sysclk 12 5 v tolerant digital input pad system clock input: 256f s , 384f s , 512f s or 768f s l3mode 13 5 v tolerant digital input pad l3-bus mode input or mode selection input l3clock 14 5 v tolerant digital input pad l3-bus/i 2 c-bus clock input or clock selection input l3data 15 5 v tolerant open drain input/output l3-bus/i 2 c-bus data input/output or format selection input bck 16 5 v tolerant digital input pad bit clock input ws 17 5 v tolerant digital input pad word select input datao 18 5 v tolerant 2 ma slew rate controlled digital output data output datai 19 5 v tolerant digital input pad data input test1 20 5 v tolerant digital input pad test control input; to be connected to ground static 21 5 v tolerant digital input pad mode selection input: static pin control or l3-bus/i 2 c-bus control status 22 5 v tolerant 2 ma slew rate controlled digital output general purpose output qmute 23 5 v tolerant digital input pad quick mute input voutr 24 analog output pad dac output right v dda(dac) 25 analog supply pad dac analog supply voltage voutl 26 analog output pad dac output left v ssa(dac) 27 analog ground pad dac analog ground v ref 28 analog pad reference voltage for adc and dac
2000 jul 31 8 philips semiconductors product speci?cation audio codec uda1342ts 8 functional description 8.1 system clock the uda1342ts operates in slave mode only, this means that in all applications the system must provide the system clock. the system clock frequency is selectable and depends on the mode of operation: l3-bus/i 2 c-bus mode: 256f s , 384f s , 512f s or 768f s static pin mode: 256f s or 384f s . the system clock must be locked in frequency to the digital interface signals. remarks: the bit clock frequency f bck can be up to 128f s , or in other words the bit clock frequency is 128 times the word select frequency f ws or less: f bck 128f ws the ws edge must fall on the negative edge of the bck signal at all times for proper operation of the digital interface the uda1342ts operates with sample frequencies from 16 to 110 khz, however for a system clock of 768f s the sampling frequency must be limited to 55 khz. 8.2 adc analog front-end the analog front-end of the uda1342ts consists of two stereo adcs with a programmable gain stage (gain from 0 to 24 db with 3 db steps) which can be controlled via the l3-bus/i 2 c-bus interface. 8.2.1 a pplication with 2 v (rms) input in applications in which a 2 v (rms) input signal is used, a15k w resistor must be used in series with the input of the adc (see fig.3). this forms a voltage divider together with the internal adc resistor and ensures that only 1 v (rms) maximum is input to the ic. using this application for a 2 v (rms) input signal, the gain switch must be set to 0 db. when a 1 v (rms) input signal is input to the adc in the same application, the gain switch must be set to 6 db. an overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in table 1. table 1 application modes using input gain stage handbook, halfpage v ssa(adc) vinl1 v dda(adc) vinr1 v adcn vinl2 v adcp vinr2 ipsel v ddd v ssd sysclk l3mode l3clock v ref v ssa(dac) voutl v dda(dac) qmute status voutr static test1 datai datao ws bck l3data 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 uda1342ts mgt017 fig.2 pin configuration. resistor (15 k w ) pga gain maximum input voltage present 0 db 2 v (rms) present 6 db 1 v (rms) absent 0 db 1 v (rms) absent 6 db 0.5 v (rms) handbook, halfpage mgt018 v ref vinl1, vinr1, vinl2, vinr2 2, 4, 6, 8 gain = 0 db 10 k w 10 k w 15 k w input signal 2 v (rms) uda1342ts fig.3 schematic of adc front-end.
2000 jul 31 9 philips semiconductors product speci?cation audio codec uda1342ts 8.2.2 d ouble differential mode since the uda1342ts is equipped with two stereo adcs, these two pairs of stereo adcs can be used to convert a single stereo signal to a signal with a higher performance by using the adcs in the double differential mode. this mode and the input signals, being channel 1 or 2 as input to the double differential configuration, can be selected via the l3-bus/i 2 c-bus interface. 8.3 decimation ?lter (adc) the decimation from 64f s to 1f s is performed in two stages. the first stage realizes a characteristic with a decimation factor of 8. the second stage consists of three half-band filters, each decimating by a factor of 2. the filter characteristics are shown in table 2. table 2 decimation ?lter characteristics 8.4 digital mixer (adc) the two stereo adc outputs are mixed with gain coefficients from +24 to - 63.5 db to be set via the microcontroller interface. in front of the mixer there is a dc filter. in order to prevent clipping, it is needed to filter out the dc component before mixing or amplifying the signals. the mixing function can be enabled via the microcontroller interface. 8.5 interpolation ?lter (dac) the digital interpolation filter interpolates from 1f s to 64f s by means of a cascade of fir filters. the filter characteristics are shown in table 3. table 3 interpolation ?lter characteristics 8.6 mute muting the dac will result in a cosine roll-off soft mute, using 32 32 = 1024 samples in the normal mode: this results in 24 ms at f s = 44.1 khz. the cosine roll-off curve is illustrated in fig.4. this cosine roll-off functions are implemented in the dac data path before the digital mixer and before the master mute (see fig.5). in the l3-bus and i 2 c-bus mode, the setting of the master mute can be overruled always by pin qmute. this quick mute uses the same cosine roll-off, but now for only 32 samples: this is 750 m s at f s = 44.1 khz. 8.7 digital mixer (dac) the adc output signal and the digital interface input signal can be mixed without an external dsp (see fig.5). this mixer can be controlled via the microcontroller interface. in order to prevent clipping when mixing two 0 db signals, the signals are attenuated digitally by - 6 db before mixing. after mixing the signal is gained by 6 db after the master volume. this way clipping at the digital mixer is prevented. after the 6 db gain, the signals can clip again, but this clipping can be removed by decreasing the master volume. item condition value (db) pass-band ripple 0 to 0.45f s 0.01 pass-band droop 0.45f s - 0.2 stop band >0.55f s - 70 dynamic range 0 to 0.45f s >135 item condition value (db) pass-band ripple 0 to 0.45f s 0.025 stop band >0.55f s - 60 dynamic range 0 to 0.45f s >135 x sin x ----------- ? ?? 4 handbook, halfpage 010 51525 1 0 0.8 mgu119 20 0.6 0.4 0.2 t (ms) mute factor fig.4 mute as a function of raised cosine roll-off.
2000 jul 31 10 philips semiconductors product speci?cation audio codec uda1342ts handbook, full pagewidth mgt019 bass boost and treble volume and mute de-emphasis volume and mute master volume and mute to digital interface output from digital interface input from decimation filter to interpolation filter + + fig.5 digital mixer (dac). 8.8 noise shaper the 5th-order noise shaper operates at 64f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter (fsdac). 8.9 filter stream dac the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post-filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac is proportionally to the power supply voltage. 8.10 digital interface the uda1342ts supports the following data input/output formats for the various modes (see fig.6). l3-bus and i 2 c-bus mode: i 2 s-bus format with data word length of up to 24 bits msb-justified serial format with data word length of up to 24 bits lsb-justified serial format with data word lengths of 16, 20 or 24 bits msb-justified data output and lsb-justified 16, 20 and 24 bits data input. static pin mode: i 2 s-bus format with data word length of up to 24 bits msb-justified data output and lsb-justified 16, 20 and 24 bits data input.
2000 jul 31 11 philips semiconductors product speci?cation audio codec uda1342ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 mgt020 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb-justified format ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 > = 8 > = 8 bck data fig.6 serial interface input/output formats.
2000 jul 31 12 philips semiconductors product speci?cation audio codec uda1342ts 8.11 sampling speed the uda1342ts operates with sample frequencies from 16 to 110 khz. this range holds for the codec as a whole. the dac part can be configured in the l3-bus and i 2 c-bus mode to accept 2 times and even 4 times the data speed (e.g. f s is 96 or 192 khz), but in these modes not all of the features can be used. some examples of the input oversampling rate settings are shown in table 4. important: in the double speed mode an input signal of 0 db is allowed, but in the quad speed mode the input signal must be limited to - 6 db to prevent the system from clipping. table 4 examples of the input oversampling rate settings system clock system clock frequency setting sampling frequency (khz) input over- sampling rate features supported 12.288 mhz (256 48 khz) 256f s 48 single speed all 96 double speed only master volume and mute 192 quad speed no features 22.5792 mhz (512 44.1 khz) 512f s 44.1 single speed all 256f s 88.2 single speed all 176.4 double speed only master volume and mute 33.8688 mhz (768 44.1 khz) 768f s 44.1 single speed all 384f s 88.2 single speed all 176.4 double speed only master volume and mute 8.12 power-on reset the uda1342ts has an internal power-on reset circuit (see fig.7) which resets the test control block. all the digital sound processing features and the system controlling features are set to their default setting in the l3-bus and i 2 c-bus mode. the reset time (see fig.8) is determined by an external capacitor which is connected between pin v ref and ground. the reset time should be at least 1 m s for v ref < 1.25 v. when v dda(dac) is switched off, the device will be reset again for v ref < 0.75 v. during the reset time the system clock should be running. handbook, halfpage v dda(dac) v ref 3.0 v 25 28 mgu001 uda1342ts c1 > 10 m f reset circuit 8 k w 8 k w fig.7 power-on reset circuit.
2000 jul 31 13 philips semiconductors product speci?cation audio codec uda1342ts handbook, halfpage 3.0 v ddd (v) 1.5 0 t 3.0 v dda(dac) (v) 1.5 0 t 3.0 v ref (v) 1.5 1.25 0.75 0 t mgu002 > 1 m s fig.8 power-on reset timing. 8.13 control modes the control mode can be set with pin static and pin l3mode: static pin mode i 2 c-bus mode l3-bus mode. table 5 mode selection the pin functions in the various modes are summarized in table 6. table 6 pin function in the selected mode all features in the l3-bus and i 2 c-bus mode are explained in sections 8.15 and 8.16. pin static pin l3mode selection low - l3-bus mode high low i 2 c-bus mode high high static pin mode pin name function l3-bus mode i 2 c-bus mode static pin mode l3clock l3clock scl clock select l3mode l3mode low level high level l3data l3data sda format select qmute qmute qmute format select ipsel a0 a0 channel select
2000 jul 31 14 philips semiconductors product speci?cation audio codec uda1342ts 8.14 static pin mode the controllable features in the static pin mode are: system clock frequency data input and output format select adc input channel select. 8.14.1 s ystem clock setting select in the static pin mode pin l3clock is used to select the system clock setting. table 7 system clock setting 8.14.2 d igital interface format select in the static pin mode the digital interface audio formats can be selected via pins l3data and qmute. the following interface formats can be selected (see table 8): i 2 s-bus format with data word length of up to 24 bits msb-justified output format and lsb-justified input format with data word length of 16, 20 or 24 bits. table 8 data format select in static pin mode 8.14.3 adc input channel select in the static pin mode pin ipsel selects the adc input channel. table 9 adc input channel select 8.15 l3-bus interface all digital processing features and system controlling features of the ud1342ts can be controlled by a microcontroller via the l3-bus interface. the controllable features are: reset system clock frequency data input and output format multi purpose output adc features C operation mode control C polarity control C input amplifier gain control C mixer control C dc filtering. dac features C power control C polarity control C input data oversampling rate C mixer position selection C mixer control C silence detector C de-emphasis C volume C flat/min./max. switch C bass boost C treble C mute C quick mute mode. 8.15.1 i ntroduction the exchange of data and control information between the microcontroller and the uda1342ts is accomplished through a serial hardware interface comprising the following pins: l3data: microcontroller interface data line l3mode: microcontroller interface mode line l3clock: microcontroller interface clock line. the uda1342ts acts as a slave receiver or a slave transmitter. therefore l3clock and l3mode lines transfer only input data and the l3data line transfers bidirectional data. pin l3clock system clock setting 0 256f s 1 384f s pin l3data pin qmute input/output format 00i 2 s 0 1 lsb-justi?ed 16 bits input and msb-justi?ed output 1 0 lsb-justi?ed 20 bits input and msb-justi?ed output 1 1 lsb-justi?ed 24 bits input and msb-justi?ed output pin ipsel channel select 0 input channel 1 (pins vinl1 and vinr1) 1 input channel 2 (pins vinl2 and vinr2)
2000 jul 31 15 philips semiconductors product speci?cation audio codec uda1342ts information transfer via the microcontroller bus is organized lsb first and in accordance with the so called l3 format, in which two different modes of operation can be distinguished: address mode and data transfer mode. important: when the device is powered-up, at least one l3clock pulse must be sent to the l3-bus interface to wake-up the interface prior to sending information to the device. this is only needed once after the device is powered-up. inside the microcontroller there is a hand-shake mechanism which handles proper data transfer from the microcontroller clock to destination clock domains. this means that when data is sent to the microcontroller interface, the system clock must be running. the l3-bus interface is designed in such a way that data is clocked into the device (write mode) on the positive clock edge, while the device starts the output data (read mode) on the negative clock edge. the microcontroller must read the data from the device on the positive clock edge to ensure the data is always stable. 8.15.2 d evice addressing the device address mode is used to select a device for subsequent data transfer. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 bits. the fundamental timing in the address mode is shown in fig.13. the device address consists of one byte, which is split up in two parts (see table 10): bits 0 and 1 are called data operation mode (dom) bits and represent the type of data transfer bits 2 to 7 represent a 6-bit device address. table 10 l3-bus interface slave address the uda1342ts can be set to different addresses (00 1000 or 10 1000) by setting pin ipsel to high or low level. in the event that the device receives a different address, it will deselect its microcontroller interface logic. basically, 2 types of data transfer can be defined: data transfer to the device and data transfer from the device (see table 11). table 11 selection of data transfer 8.15.3 r egister addressing after sending the device address, including the flags (dom bits) whether the information is read or written, the data transfer mode is entered and one byte is sent with the destination register address (see table 12) using 7 bits, and one bit which signals whether information will be read or written. the fundamental timing for the data transfer mode is given in fig.14. table 12 l3-bus register address basically there are 3 cases for register addressing: 1. register addressing for l3-bus write: the first bit is at logic 0 indicating a write action to the destination register, and is followed by 7 bits indicating the register address. 2. prepare read addressing: the first bit of the byte is at logic 1, signalling data will be read from the register indicated. 3. read action itself: in this case the device returns a register address prior to sending data from that register. when the first bit of the byte is at logic 0, the register address was valid and if the first bit is at logic 1 the register address was invalid. important: 1. each time a new destination address needs to be written, the device address must be sent again. 2. when addressing the device for the first time after power-up of the device, at least one l3clock cycle must be given to enable the l3-bus interface. dom device address lsb bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 msb r/ w 1 ipsel 01000 dom transfer bit 0 bit 1 0 0 not used 1 0 not used 0 1 data write or prepare read 1 1 data read lsb bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 msb r/ wa6a5a4a3a2a1a0
2000 jul 31 16 philips semiconductors product speci?cation audio codec uda1342ts 8.15.4 d ata write mode the data write format is given in table 13 and illustrated in fig.9. when writing data to a device four bytes must be sent: 1. one byte with the device address, being 01x0 1000 where x stands for the ipsel value, including 01 for signalling write to the device. 2. one byte starting with a logic 0 for signalling write followed by 7 bits indicating the register address. 3. one byte which is the most significant data (msd) byte 1. 4. one byte which is the least significant data (lsd) byte 2. 8.15.5 d ata read mode the data write format is given in table 14 and illustrated in fig.10. when reading from the device, a prepare read must first be done. after the prepare read, the device address is sent again. the device then returns with the register address, indicating whether the address was valid or not, and the data of the register. the data read mode is explained below: 1. one byte with the device address, being 01x0 1000 where x stands for the ipsel value, including 01 for signalling write to the device. 2. one byte is sent with the register address which needs to be read. this byte starts with a logic 1, which indicates that there will be a read action from the register. 3. one byte with the device address including 11 is sent to the device. the 11 indicates that the device must write data to the microcontroller. 4. the device now writes the requested register address on the l3-bus, indicating whether the requested register was valid (logic 0) or invalid (logic 1). 5. the device writes data from the requested register to the l3-bus with the msd byte 1 first, followed by the lsd byte 2. table 13 l3-bus format for data write table 14 l3-bus format for prepare read and read data l3mode data type first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 address device address 0 1 ipsel 01000 data transfer 1 register address 0 a6 a5 a4 a3 a2 a1 a0 data transfer 2 msd byte 1 d15 d14 d13 d12 d11 d10 d9 d8 data transfer 3 lsd byte 2 d7 d6 d5 d4 d3 d2 d1 d0 l3mode data type first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 prepare read address device address 0 1 ipsel 01000 data transfer 1 register address 1 a6 a5 a4 a3 a2 a1 a0 read data address device address 1 1 ipsel 01000 data transfer 1 register address 0/1 a6 a5 a4 a3 a2 a1 a0 data transfer 2 msd byte 1 d15 d14 d13 d12 d11 d10 d9 d8 data transfer 3 lsd byte 2 d7 d6 d5 d4 d3 d2 d1 d0
2000 jul 31 17 philips semiconductors product speci?cation audio codec uda1342ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mgs753 l3clock l3mode l3data 0 write l3 wake-up pulse after power-up device address dom bits register address data byte 1 data byte 2 10 fig.9 data write mode for l3-bus version 2. mgs754 l3clock l3mode l3data 0 read valid/non-valid device address prepare read send by the device dom bits register address device address register address data byte 1 data byte 2 111 0/1 1 fig.10 data read mode for l3-bus version 2.
2000 jul 31 18 philips semiconductors product speci?cation audio codec uda1342ts 8.16 i 2 c-bus interface besides the l3-bus mode the uda1342ts supports the i 2 c-bus mode; all the features can be controlled by the microcontroller with the same register addresses as used in the l3-bus mode. the exchange of data and control information between the microcontroller and the uda1342ts in the i 2 c-bus mode is accomplished through a serial hardware interface comprising the following pins and signals: l3clock: serial clock line (scl) l3data: serial data line (sda). the clock and data timing of the i 2 c-bus transfer is shown in fig.15. 8.16.1 a ddressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure (s). 8.16.2 s lave address the uda1342ts acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal. the data signal sda is an input or output signal (bidirectional line). the uda1342ts slave address format is shown in table 15. table 15 i 2 c-bus slave address format the slave address bit ipsel corresponds to the hardware address pin ipsel which allows selecting the slave address. 8.16.3 r egister address the uda1342ts register address format is given in table 16. table 16 i 2 c-bus register address format the register mapping of the i 2 c-bus and l3-bus interfaces is the same (see section 9). msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb 001101 ipsel r/ w msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb 0 a6a5a4a3a2a1a0
2000 jul 31 19 philips semiconductors product speci?cation audio codec uda1342ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8.16.4 w rite cycle the write cycle is used to write data from the microcontroller to the internal registers. the i 2 c-bus format for a write cycle is shown in table 17. the device and register addresses are one byte each, data is always two bytes (2-bytes data). the format of the write cycle is as follows: 1. the microcontroller starts with a start condition s. 2. the first byte (8 bits) contains the device address 0011 01x and a write command (bit r/ w = 0). 3. this is followed by an acknowledge (a) from the uda1342ts. 4. the microcontroller then writes the register address (8 bits) where writing of the register content of the uda1342ts must star t. 5. the uda1342ts acknowledges this register address. 6. the microcontroller sends 2-bytes data with the most significant data (msd) byte first and then the least significant data (lsd) byte, where each byte is acknowledged by the uda1342ts. 7. after the last acknowledge the uda1342ts frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 17 master transmitter writes to uda1342ts registers note 1. auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted. acknowledge from uda1342ts device address r/ w register address data (1) s 0011 01x 0 a 0xxx xxxx a msd1 a lsd1 a msd2 a lsd2 a msdn a lsdn a p 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits
2000 jul 31 20 philips semiconductors product speci?cation audio codec uda1342ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8.16.5 r ead cycle the read cycle is used to read data from the internal registers of the uda1342ts to the microcontroller. the i 2 c-bus format for a read cycle is shown in table 18. the format of the read cycle is as follows: 1. the microcontroller starts with a start condition s. 2. the first byte (8 bits) contains the device address 0011 01x and a write command (bit r/ w = 0). 3. this is followed by an acknowledge (a) from the uda1342ts. 4. the microcontroller then writes the register address where reading of the register content of the uda1342ts must start. 5. the uda1342ts acknowledges this register address. 6. then the microcontroller generates a repeated start (sr). 7. again the device address 0011 01x is given, but this time followed by a read command (bit r/ w = 1). 8. the uda1342ts sends the two-byte data with the most significant data (msd) byte first and then the least significant data (ls d) byte, where each byte is acknowledged by the microcontroller (master). 9. the microcontroller stops this cycle by generating a negative acknowledge (na). 10. the uda1342ts then frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 18 master transmitter reads from uda1342ts registers note 1. auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted. acknowledge from uda1342ts acknowledge from master device address r/ w register address device address r/ wdata (1) s 0011 01x 0 a 0xxx xxxx a sr 0011 01x 1 a msd1 a lsd1 a msd2 a lsd2 a msdn a lsdn na p 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits
2000 jul 31 21 philips semiconductors product speci?cation audio codec uda1342ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 9 register mapping the addresses of the control registers with default values at power-on reset are shown in table 19. functions of the registers a re shown in tables 20 to 45. table 19 register map address function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00h system rst qs mdc dc am2 am1 am0 pad 0 sc1 sc0 if2 if1 if0 dp pda - 001101000000010 01h sub system -------- os1 os0 mps mix sd1 sd0 mp1 mp0 -------- 00000000 02h to 0fh reserved ---------------- 10h dac features m1 m0 bb3 bb2 bb1 bb0 tr1 tr0 sds mtb mta mt qm de2 de1 de0 0000000000000000 11h dac master volume vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 vr7 vr6 vr5 vr4 vr3 vr2 vr1 vr0 0000000000000000 12h dac mixer volume vb7 vb6 vb5 vb4 vb3 vb2 vb1 vb0 va7 va6 va5 va4 va3 va2 va1 va0 0000000000000000 13h to 1fh reserved ---------------- 20h adc input and mixer gain channel 1 0 0 0 0 ia3 ia2 ia1 ia0 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 0000000000000000 21h adc input and mixer gain channel 2 0 0 0 0 ib3 ib2 ib1 ib0 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 0000000000000000 22h to 2fh reserved ---------------- 30h evaluation 0 0 0 0000000000000 31h to ffh reserved ----------------
2000 jul 31 22 philips semiconductors product speci?cation audio codec uda1342ts 9.1 reset a 1-bit value to initialize the l3-bus and i 2 c-bus registers except the system register (00h) with default settings by setting bit rst = 1. table 20 reset bit 9.2 quick mode switch a 1-bit value to enable the quick mode change of the adc. the soft mode change works only between modes if bit am2 = 1. table 21 quick mode switch 9.3 bypass mixer dc ?lter a 1-bit value to disable the dc filter of the adc mixer. this dc filter is in front of the mixer to prevent clipping inside the mixer due to dc signals. table 22 mixer dc ?ltering 9.4 dc ?lter a 1-bit value to enable the dc filter of the adc output. this dc filter is inside the decimation filter. table 23 dc-?ltering 9.5 adc mode a 3-bit value to select the mode of the adc. table 24 adc mode 9.6 adc polarity a 1-bit value to control the adc polarity. table 25 polarity control of the adc 9.7 system clock frequency a 2-bit value to select the external clock frequency. table 26 system clock frequency settings rst function 0 no reset 1 reset registers to default qs function 0 soft mode change 1 quick mode change mdc function 0 enable mixer dc ?ltering 1 disable mixer dc ?ltering dc function 0 disable output dc ?ltering 1 enable output dc ?ltering am2 am1 am0 function 0 0 0 adc power-off 0 0 1 input 1 select (input 2 off) 0 1 0 input 2 select (input 1 off) 0 1 1 not used 1 0 0 channel swap and signal inversion 1 0 1 input 1 select (double differential mode) 1 1 0 input 2 select (double differential mode) 1 1 1 mixing mode pad function 0 non-inverting 1 inverting sc1 sc0 function 0 0 256f s 0 1 384f s 1 0 512f s 1 1 768f s
2000 jul 31 23 philips semiconductors product speci?cation audio codec uda1342ts 9.8 data format a 3-bit value to select the data format. table 27 data format selection 9.9 dac power control a 1-bit value to disable the dac to reduce power consumption. the dac power-off is not recommended when the dac outputs are dc loaded. table 28 dac power control 9.10 input oversampling rate a 2-bit value to select the oversampling rate of the input signal (see table 32). in the quad speed input rate, care must be taken that the input signal is smaller than - 5.67 db (fs). 9.11 dac polarity a 1-bit value to control the dac polarity. table 29 polarity control of dac 9.12 dac mixing position switch a 1-bit value to select the mixing position of the adc signal in the dac. table 30 dac mixing position switch 9.13 dac mixer a 1-bit value to enable the digital mixer of the dac. table 31 dac mixer if2 if1 if0 function 000i 2 s-bus 0 0 1 lsb-justi?ed16 bits 0 1 0 lsb-justi?ed 20 bits 0 1 1 lsb-justi?ed 24 bits 1 0 0 msb-justi?ed 1 0 1 lsb-justi?ed 16 bits input and msb-justi?ed output 1 1 0 lsb-justi?ed 20 bits input and msb-justi?ed output 1 1 1 lsb-justi?ed 24 bits input and msb-justi?ed output dp function 0 dac power-off 1 dac power-on pda function 0 non-inverting 1 inverting mps function 0 before sound features 1 after sound features mix function 0 disable mixer 1 enable mixer table 32 input oversampling rate os1 os0 mode sampling frequency adc dac features 0 0 single speed 16 to 110 khz supported all digital ?lters and all features, including mixing are available 0 1 double speed 32 to 220 khz not supported ?rst digital ?lter is bypassed, only master volume and master mute features are available 1 0 quad speed 64 to 440 khz not supported no mixing nor any sound feature is supported 1 1 reserved -- -
2000 jul 31 24 philips semiconductors product speci?cation audio codec uda1342ts 9.14 silence detection period a 2-bit value to define the silence period for the silence detector. table 33 silence detection period 9.15 multi purpose output a 2-bit value to select the output signal on pin status. table 34 multi purpose output selection 9.16 mode a 2-bit value to program the mode of the sound processing filters of bass boost and treble. table 35 flat/min./max. switch position 9.17 bass boost a 4-bit value to program the bass boost settings. the used set depends on the setting of bits m1 and m0. at f s = 44.1 khz the - 3 db point for minimum setting is 250 hz and the - 3 db point for maximum setting is 300 hz. the default value is 0000. table 36 bass boost settings 9.18 treble a 2-bit value to program the treble setting. the used set depends on the setting of bits m1 and m0. at f s = 44.1 khz the - 3 db point for minimum setting is 3.0 khz and the - 3 db point for maximum setting is 1.5 khz. the default value is 00. table 37 treble settings sd1 sd0 function 0 0 3200 samples 0 1 4800 samples 1 0 9600 samples 1 1 19200 samples mp1 mp0 function 0 0 no output 0 1 over?ow (adc) detection 1 0 reserved 1 1 digital silence detection m1 m0 function 0 0 ?at 0 1 min. 1 0 min. 1 1 max. bb3 bb2 bb1 bb0 bass boost (db) flat min. max. 0000000 0001022 0010044 0011066 0100088 010101010 011001212 011101414 100001616 100101818 101001820 101101822 110001824 110101824 111001824 111101824 tr1 tr0 treble (db) flat min. max. 00 0 0 0 01 0 2 2 10 0 4 4 11 0 6 6
2000 jul 31 25 philips semiconductors product speci?cation audio codec uda1342ts 9.19 silence detector switch a 1-bit value to enable the silence detector. table 38 silence detector switch 9.20 mute three 1-bit values to enable the digital mute. bit mt is the master mute, using bit mta the signal from the digital interface can be soft muted when the dac mixer is enabled and using bit mtb the signal from adc can be soft muted. table 39 mute 9.21 quick mute mode a 1-bit value to enable the quick mute function of the master mute. table 40 quick mute mode settings 9.22 de-emphasis a 3-bit value to enable the digital de-emphasis filter. table 41 de-emphasis settings 9.23 adc input ampli?er gain two 4-bit values to program the gain of the input amplifiers. bits ia applies for input amplifier a and bits ib to input amplifier b. table 42 adc input ampli?er gain settings sds function 0 disable silence detector 1 enable silence detector mt mta mtb function 0 no muting 1 muting qm function 0 soft mute mode 1 quick mute mode de2 de1 de0 function 0 0 0 no de-emphasis 0 0 1 de-emphasis at f s = 32 khz 0 1 0 de-emphasis at f s = 44.1 khz 0 1 1 de-emphasis at f s = 48 khz 1 0 0 de-emphasis at f s = 96 khz ia3 ib3 ia2 ib2 ia1 ib1 ia0 ib0 amplifier gain (db) 0000 0 0001 3 0010 6 0011 9 0100 12 0101 15 0110 18 0111 21 1000 24
2000 jul 31 26 philips semiconductors product speci?cation audio codec uda1342ts 9.24 dac volume control four 8-bit values to program the volume attenuations. the range is from 0 to - 66 db and - db in steps of 0.25 db. bits vl and vr are master volumes for the left and right channels. table 43 dac volume settings 9.25 dac mixer volume control four 8-bit values to program the volume attenuations. the range is from 0 to - 60 db and - db in steps of 0.25 db. when the dac mixer is enabled, the signal from the digital interface can be controlled by bits va and the signal from the adc can be controlled by bits vb. table 44 dac volume settings vl7 vr7 vl6 vr6 vl5 vr5 vl4 vr4 vl3 vr3 vl2 vr2 vl1 vr1 vl0 vr0 volume (db) 00000000 0 00000001 - 0.25 00000010 - 0.50 00000011 - 0.75 00000100 - 1.00 :::::::: : 11000100 - 49.0 11000101 - 49.25 11000110 - 49.5 11000111 - 49.75 11001000 - 50.0 11001100 - 52.0 11010000 - 54.0 11010100 - 57.0 11011000 - 60.0 11011100 - 66.0 11100000 - :::::::: : 11111111 - va7 vb7 va6 vb6 va5 vb5 va4 vb4 va3 vb3 va2 vb2 va1 vb1 va0 vb0 volume (db) 00000000 0 00000001 - 0.25 00000010 - 0.50 00000011 - 0.75 00000100 - 1.00 :::::::: : 10101100 - 43.0 10101101 - 43.25
2000 jul 31 27 philips semiconductors product speci?cation audio codec uda1342ts 9.26 adc mixer gain control two 8-bit values to program the channel 1 and 2 mixing, when the mixer mode is selected. bits ma applies to channel 1 and bits mb to channel 2. the range is from +24 to - 63.5 db and - db in steps of 0.5 db. table 45 adc mixer gain settings 10101110 - 43.5 10101111 - 43.75 10110000 - 44.0 10110100 - 46.0 10111000 - 48.0 10111100 - 51.0 11000000 - 54.0 11000100 - 60.0 11001000 - :::::::: : 11111111 - ma7 mb7 ma6 mb6 ma5 mb5 ma4 mb4 ma3 mb3 ma2 mb2 ma1 mb1 ma0 mb0 mixer gain (db) 00110000 +24.0 00101111 +23.5 00101110 +23.0 :::::::: : 00000010 +1.0 00000001 +0.5 00000000 0 11111111 - 0.5 :::::::: : 10000100 - 62.0 10000011 - 62.5 10000010 - 63.0 10000001 - 63.5 10000000 - va7 vb7 va6 vb6 va5 vb5 va4 vb4 va3 vb3 va2 vb2 va1 vb1 va0 vb0 volume (db)
2000 jul 31 28 philips semiconductors product speci?cation audio codec uda1342ts 10 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all supply connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor via a 0.75 m h series inductor. 4. dac operation after short-circuiting cannot be warranted. 11 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. 12 quality specification in accordance with snw-fq-611-e . 13 thermal characteristics 14 dc characteristics v ddd =v dda(adc) =v dda(dac) = 3.0 v; t amb =25 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage note 1 - 4v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v es electrostatic handling voltage note 2 - 1100 +1100 v note 3 - 250 +250 v i lu(prot) latch-up protection current t amb = 125 c; v dd = 3.6 v - 200 ma i sc(dac) short-circuit current of dac t amb =0 c; v dd = 3 v; note 4 output short-circuited to v ssa(dac) - 450 ma output short-circuited to v dda(dac) - 325 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 90 k/w symbol parameter conditions min. typ. max. unit supplies; note 1 v dda(adc) adc analog supply voltage 2.7 3.0 3.6 v v dda(dac) dac analog supply voltage 2.7 3.0 3.6 v v ddd digital supply voltage 2.7 3.0 3.6 v
2000 jul 31 29 philips semiconductors product speci?cation audio codec uda1342ts notes 1. all supply connections must be made to the same power supply unit. 2. v dda =v dda(dac) =v dda(adc) . 3. when higher capacitive loads must be driven, a 100 w resistor must be connected in series with the dac output in order to prevent oscillations in the output operational amplifier. i dda(adc) adc analog supply current 1 ad c + 1 pga enabled - 10 - ma 2 adcs + 2 pgas enabled - 20 - ma all adcs + all pgas power-down - 200 -m a i dda(dac) dac analog supply current operating - 6.0 - ma dac power-down - 250 -m a i ddd digital supply current operating - 9.0 - ma adc power-down - 4.5 - ma dac power-down - 5.5 - ma digital input pins (5 v tolerant ttl compatible) v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage - 0.5 - +0.8 v ? i li ? input leakage current -- 1 m a c i input capacitance -- 10 pf digital output pins v oh high-level output voltage i oh = - 2 ma 0.85v ddd -- v v ol low-level output voltage i ol =2ma -- 0.4 v reference voltage v ref reference voltage with respect to v ssa(adc) ; note 2 0.45v dda 0.5v dda 0.55v dda v r o(vref) output resistance on pin v ref - 5 - k w analog-to-digital converter v adcp positive reference voltage of the adc - v dda(adc) - v v adcn negative reference voltage of the adc - 0.0 - v r i input resistance - 10 - k w c i input capacitance - 24 - pf digital-to-analog converter i o(max) maximum output current (thd + n)/s < 0.1% - 1.6 - ma r l load resistance 3 -- k w c l load capacitance note 3 -- 50 pf symbol parameter conditions min. typ. max. unit
2000 jul 31 30 philips semiconductors product speci?cation audio codec uda1342ts 15 ac characteristics v ddd =v dda(adc) =v dda(dac) = 3.0 v; f i = 1 khz at - 1 db; t amb =25 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit analog-to-digital converter v i(rms) input voltage (rms value) 0 db setting - 900 - mv 3 db setting - 640 - mv 6 db setting - 450 - mv 9 db setting - 320 - mv 12 db setting - 225 - mv 15 db setting - 160 - mv 18 db setting - 122.5 - mv 21 db setting - 80 - mv 24 db setting - 61.25 - mv d v i unbalance between channels - <0.1 - db (thd + n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s = 48 khz normal mode; at - 1db 0 db setting -- 90 - db 3 db setting -- 90 - db 6 db setting -- 90 - db 9 db setting -- 90 - db 12 db setting -- 89 - db 15 db setting -- 89 - db 18 db setting -- 88 - db 21 db setting -- 87 - db 24 db setting -- 85 - db normal mode; at - 60 db; a-weighted 0 db setting -- 40 - db 3 db setting -- 37 - db 6 db setting -- 36 - db 9 db setting -- 35 - db 12 db setting -- 33 - db 15 db setting -- 31 - db 18 db setting -- 30 - db 21 db setting -- 28 - db 24 db setting -- 26 - db double differential mode at 0 db gain -- 93 - db at 0 db gain; - 60 db input; a-weighted -- 41 - db
2000 jul 31 31 philips semiconductors product speci?cation audio codec uda1342ts (thd + n)/s 96 total harmonic distortion-plus-noise to signal ratio at f s = 96 khz normal mode at 0 db gain -- 84 - db at - 60 db; a-weighted -- 39 - db s/n 48 signal-to-noise ratio at f s = 48 khz v i = 0 v; a-weighted normal mode - 100 - db double differential mode - 101 - db s/n 96 signal-to-noise ratio at f s = 96 khz v i = 0 v; a-weighted; normal mode - 99 - db a cs channel separation - 100 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - 30 - db digital-to-analog converter v o(rms) output voltage (rms value) at 0 db (fs) digital input - 0.9 - v d v o unbalance between channels - <0.1 - db (thd+n)/s 48 total harmonic distortion-plus-noise to signal ratio at f s = 48 khz at 0 db -- 90 - db at - 60 db; a-weighted -- 40 - db (thd+n)/s 96 total harmonic distortion-plus-noise to signal ratio at f s = 96 khz at 0 db -- 83 - db at - 60 db; a-weighted -- 39 - db s/n 48 signal-to-noise ratio at f s = 48 khz code = 0; a-weighted - 100 - db s/n 96 signal-to-noise at f s = 96 khz code = 0; a-weighted - 99 - db a cs channel separation - 100 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - 60 - db symbol parameter conditions min. typ. max. unit
2000 jul 31 32 philips semiconductors product speci?cation audio codec uda1342ts 16 timing v ddd =v dda(adc) =v dda(dac) = 2.7 to 3.6 v; t amb = - 20 to +85 c; all voltages referenced to ground; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit system clock timing; note 1 (see fig.11) t sys system clock cycle time f sys = 256f s 35 81 250 ns f sys = 384f s 23 54 170 ns f sys = 512f s 17 41 130 ns f sys = 768f s 17 27 90 ns t cwl system clock low time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns t cwh system clock high time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns serial interface input/output data timing (see fig.12) f bck bit clock frequency -- 128f s hz t cy(bck) bit clock cycle time t cy(s) = sample frequency cycle time -- 1 128 t cy(s) s t bckh bit clock high time 30 -- ns t bckl bit clock low time 30 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(ws) word select set-up time 10 -- ns t h(ws) word select hold time 10 -- ns t su(datai) data input set-up time 10 -- ns t h(datai) data input hold time 10 -- ns t h(datao) data output hold time 0 -- ns t d(datao-bck) data output to bit clock delay -- 30 ns t d(datao-ws) data output to word select delay -- 30 ns l3-bus interface timing (see figs 13 and 14) t r rise time note 2 -- 10 ns/v t f fall time note 2 -- 10 ns/v t cy(clk)l3 l3clock cycle time note 3 500 -- ns t clk(l3)h l3clock high time 250 -- ns t clk(l3)l l3clock low time 250 -- ns t su(l3)a l3mode set-up time in address mode 190 -- ns t h(l3)a l3mode hold time in address mode 190 -- ns t su(l3)d l3mode set-up time in data transfer mode 190 -- ns t h(l3)d l3mode hold time in data transfer mode 190 -- ns
2000 jul 31 33 philips semiconductors product speci?cation audio codec uda1342ts notes 1. the typical value of the timing is specified at 48 khz sampling frequency. 2. in order to prevent digital noise interfering with the l3-bus communication, it is best to have the rise and fall times as small as possible. 3. when the sampling frequency is below 32 khz, the l3clock cycle must be limited to 1 64fs cycle. 4. c b is the total capacitance of one bus line in pf. the maximum capacitive load for each bus line is 400 pf. 5. after this period, the first clock pulse is generated. 6. to be suppressed by the input filter. t stp(l3) l3mode stop time in data transfer mode 190 -- ns t su(l3)da l3data set-up time in address and data transfer mode 190 -- ns t h(l3)da l3data hold time in address and data transfer mode 30 -- ns t su(l3)r l3data set-up time for read data 50 -- ns t h(l3)r l3data hold time for read data 360 -- ns t en(l3)r l3data enable time for read data 380 -- ns t dis(l3)r l3data disable time for read data 50 -- ns i 2 c-bus interface timing (see fig.15) f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 -- m s t high scl high time 0.6 -- m s t r rise time sda and scl note 4 20 + 0.1c b - 300 ns t f fall time sda and scl note 4 20 + 0.1c b - 300 ns t hd;sta hold time start condition note 5 0.6 -- m s t su;sta set-up time repeated start 0.6 -- m s t su;sto set-up time stop condition 0.6 -- m s t buf bus free time between a stop and start condition 1.3 -- m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 -- m s t sp pulse width of spikes note 6 0 - 50 ns c b capacitive load for each bus line -- 400 pf symbol parameter conditions min. typ. max. unit
2000 jul 31 34 philips semiconductors product speci?cation audio codec uda1342ts handbook, full pagewidth mgr984 t sys t cwh t cwl fig.11 timing of system clock. handbook, full pagewidth mgs756 ws bck datao datai t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(datao) t su(datai) t h(datai) t d(datao-bck) t d(datao-ws) fig.12 serial interface input data timing.
2000 jul 31 35 philips semiconductors product speci?cation audio codec uda1342ts handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.13 timing of address mode. handbook, full pagewidth t stp(l3) t su(l3)d t h(l3)da t en(l3)r t h(l3)r t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mgu015 t clk(l3)h t clk(l3)l t su(l3)r t dis(l3)r fig.14 timing of data transfer mode for write and read.
2000 jul 31 36 philips semiconductors product speci?cation audio codec uda1342ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.15 timing of the i 2 c-bus transfer.
2000 jul 31 37 philips semiconductors product speci?cation audio codec uda1342ts 17 application information handbook, full pagewidth mgt021 47 w r13 c13 100 m f (16 v) c12 100 m f (16 v) v ddd v dda l1 blm32a07 blm32a07 l2 + 3 v ground 1 v ssa(adc) uda1342ts 12 28 sysclk v ref 25 3 da 5727 v dda(adc) v adcn v adcp system clock 18 datao 16 bck 17 ws c1 r1 0 w 0 w 0 w 0 w r2 r3 r4 47 m f (16 v) 2 vinl1 26 voutl r5 100 w r11 10 k w 24 voutr r6 100 w r12 10 k w c2 47 m f (16 v) 4 vinr1 19 datai 13 l3mode 14 l3clock 15 l3data v dda v ssa(dac) v dda(dac) c7 47 m f (16 v) c6 47 m f (16 v) c5 47 m f (16 v) c20 100 nf (63 v) 23 qmute 9 ipsel 22 status 21 static 20 test1 100 nf (63 v) c9 100 m f (16 v) c22 r15 1 w 100 nf (63 v) c11 100 m f (16 v) c24 r17 220 w 100 nf (63 v) c10 100 m f (16 v) c23 r16 1 w v ddd v ssd 10 11 r14 1 w c8 100 m f (16 v) c21 100 nf (63 v) v ddd left output right output left input 1 right c3 47 m f (16 v) 6 vinl2 c4 47 m f (16 v) 8 vinr2 left input 2 right i 2 s-bus i 2 c-bus l3-bus fig.16 application diagram.
2000 jul 31 38 philips semiconductors product speci?cation audio codec uda1342ts 18 package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150 95-02-04 99-12-27 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0
2000 jul 31 39 philips semiconductors product speci?cation audio codec uda1342ts 19 soldering 19.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 19.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 19.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 jul 31 40 philips semiconductors product speci?cation audio codec uda1342ts 19.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 jul 31 41 philips semiconductors product speci?cation audio codec uda1342ts 20 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 21 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 23 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2000 jul 31 42 philips semiconductors product speci?cation audio codec uda1342ts notes
2000 jul 31 43 philips semiconductors product speci?cation audio codec uda1342ts notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 70 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753503/25/02/pp 44 date of release: 2000 jul 31 document order number: 9397 750 07241
home a bout nxp news in focus careers inves tors tech support contact my.nxp the uda1342ts is a single-chip 4 channel analog-to-digital conver ter and 2 channel digital-to-analog converter with signal proc essing features employing bitstream conversion techniques. the low po wer consumption and low voltage requirements make the device emin ently suitable for use in low-voltage low-power portable digital audio equipment which incorp orates recording and playback functions. the uda1342ts supports the i2s-bus data format with word length s of up to 24 bits, the msb-justified data format with word leng ths of up to 24 bits and the lsb-justified serial data format with word lengths of 16, 20 and 24 bits. the device also suppor ts a combination of the msb-justified output format and the lsb- justified input format. the uda1342ts has special sound processing features in the playback mode such as de-emphasis, volume, mute, bass boost and treb le, which can be controlled by the microcontroller via the l3-bus or i2c-bus interface. back to top general 2.7 to 3.6 v power supply 5 v tolerant digital inputs high pin compatibility with uda1341ts 24 bits data path selectable control via l3-bus interface, i2c- bus interface or static pin control; choice of 2 device addresses in l3-bus and i2 c-bus mode supports sample frequencies from 16 to 110 khz separate power control for adc and dac adc and programmable gain amplifiers (pga) plus in tegrated high-pass filter to cancel dc offset integrated digital filter plus dac digital silence detection uda1342ts preview detailed information parametric search datasheet uda1342ts (product specification) 31-jul-00,44 pages, 201 kb download datasheet download all documentation audio codec general description features products/packages chemical content pricing/ordering/availability samples applications block diagrams/pinning technical documents parametrics/similar products download/print/email general descri p tion hide features hide see the answers to faq's on certain fields of interest find nxp's equivalent of a competitor's part number view case studies on general applications or technologies request contact with a technical expert find more information on nxp's vision find out more about our ordering process receive e-news on specific interest areas see also a pplications looking fo r products ... audio codecs uda1342ts select site: english advanced search type search here search pa g e 1 of 4 24-ap r -2008 file://c:\docume~1\askhan\locals~1\temp\463e7rss.htm
no analog post filtering required for dac slave mode only applications easy application. multiple format data interface i2s-bus, msb-justified and lsb-justified format compatible 1f s to 4f s input and 1f s output format data rate. dac digital sound processing separate digital logarithmic volume control for left an d right channels in l3-bus mode or i2c-bus mode digital tone control, bass boost and treble in l3-bus mode or i2c-bus mode digital de-emphasis for sample frequencies of 32, 44.1, 48 and 96 khz in l3-bus mode or i2c-bus mode soft or quick mute in l3-bus mode or i2c-bus mode output signal polarity control in l3-bus mode or i2c-bus mode digital mixer for adc output signal and digital serial input signal. advanced audio configuration 4 channel (2 x stereo) single-ended inputs with programmable ga in amplifiers and 2 channel (1 x stereo) single-ended outputs co nfiguration output signal polarity control in l3-bus mode or i2c-bus mode high linearity, wide dynamic range, low distortion double differential input configurati on for enhanced adc sound quality. back to top back to top products/ p acka g es hide type number north american type number ordering code (12nc) product status package packing marking chemical content leadfree conversion date uda1342ts/n1 uda1342tsdb 9352 629 09512 volume production sot341- 1 (ssop28) tube dry pack standard marking uda1342ts/n1 week 18, 2005 uda1342ts/n1 uda1342tsdb-t 9352 629 09518 volume production sot341- 1 (ssop28) reel dry pack, smd, 13" standard marking uda1342ts/n1 week 18, 2005 pricin g /orderin g /availabilit y hide type number ordering code(12nc) indicative price/unit($) region distri butor in stock inventory date buy online samples uda1342ts/n1 9352 629 09512 na mouser electronics 1,000 4/20/2008 buy online not available pa g e 2 of 4 24-ap r -2008 file://c:\docume~1\askhan\locals~1\temp\463e7rss.htm
back to top eminently suitable for minidisc (m d) home and portable applications. back to top support documents 75007723; audio dataconversion ics (2001-11-23) 75014374_ap; audio processing () 75011122; p9xc557ex 8-bit 80c51 with up to 64 kbytes of internal program memory, 5 i/o ports and 10-bit adc (2003-03-07) back to top download this product information. email this product information. print this product information. back to top the information published on product information pages of the www. nxp.com or www.semiconductors.com websites is an extract from product data sheets and is for information purposes only. for detailed info rmation please check the most recent version of the relevant product data sheet as published on these we bsites. in the event of any conflict between product information pages and data sheets or deviations from information provided in the product data sheets on these product informati on pages, the information provided in the product data sheets shall prevail. the product status of the produ ct(s) described in the product data sheet may have changed since publication of the data sheet a nd therefore information in datasheets on product status may be outdated. the latest information on product status is published on the product information pages of the above-mentioned websites. as from october 1st, 2006 philips semiconductors has a new trade na me - nxp semiconductors, which will be used in future data s heets together with new contact details. in data sheets where the previous philips references remain, please use the new links as shown below. http://www.philips.semiconductors.com use http://www.nxp.com http://www.semiconducto rs.philips.com use http://www.nxp.com (internet) sales.addresses@www.semicond uctors.philips.com use salesaddresses@nxp.com (e-mail) the copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - ? koninklijke philips electronics n.v. (year). all rights reserved - is replaced with: - ? nxp b.v. (year). all rights reserved.- na digi-key corporation 974 4/20/2008 buy online uda1342ts/n1 9352 629 09518 order samples a pp lications hide technical documents hide download/ p rint/email hide disclaime r hide pa g e 3 of 4 24-ap r -2008 file://c:\docume~1\askhan\locals~1\temp\463e7rss.htm
nxp | privacy policy | terms of use | sitemap | switch to classic mode ?2006-2008 nxp semiconductors. all rights reserved if you have any questions related to the data sheet, please cont act our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com ). thank you for your cooperation and understanding. back to top pa g e 4 of 4 24-ap r -2008 file://c:\docume~1\askhan\locals~1\temp\463e7rss.htm

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